The present invention relates to integrated circuits and, in particular, to a new type of integrated circuit comprising active and passive devices formed in a thin slice of single crystal semiconductor bonded to a high resistivity polycrystalline silicon substrate.
Conventional integrated circuits are typically fabricated on relatively thick wafers of monocrystalline silicon. While only a thin top layer of the silicon, typically less than a micrometer in thickness, is utilized by the circuit devices, the wafers are typically about 0.5 to 0.8 mm in thickness in order to provide required mechanical rigidity. Such wafers are utilized in the fabrication of integrated circuits using a variety of technologies, including CMOS, NMOS, bipolar and BiCMOS technologies.
These conventional integrated circuits are not well suited for high frequency applications because of the relatively low resistivity of the silicon underlying the active region. With increasing switching speed of digital circuits and increasing frequency of operation of analog circuits, the underlying crystalline silicon leads to a variety of adverse parasitic effects. Specifically, the underlying silicon contributes to the parasitic capacitance of each transistor and introduces parasitic capacitance with the interconnection wires. When both digital and analog circuits are formed on the same wafer, the underlying silicon contributes to crosstalk between the two types of circuits. And when the wafer includes high frequency inductors, eddy currents induced in the substrate dampen the resonance of associated circuits and reduce the quality factor Q of the inductors.
Although various approaches have been tried to solve these problems, none have proved completely satisfactory. One approach, referred to as the silicon on insulator (SOI) technique is commonly implemented by forming the integrated circuit in a film of single crystal silicon separated from a single crystal silicon substrate by a layer of insulating silicon oxide. SOI usually improves the circuit performance, primarily by reducing parasitic capacitance of the transistors. It also may decrease the cross talk between different parts of the circuit. There are two common implementations of SOI. In the first, a high dose of oxygen is implanted into single crystalline Si and after suitable heat treatment this leads to formation of a buried insulating silicon oxide film. This process is known as the SIMOX (Separation by IMplanted OXygen) process. In the second implementation, two single crystalline Si wafers, at least one of which is coated with a layer of silicon dioxide, are bonded together and then one of the wafers is thinned until only a film of silicon remains. All these SOI wafers, whether formed by SIMOX or by bonding, typically consist of a device layer that is separated by silicon oxide (usually silicon dioxide) from a single crystalline substrate that is not intentionally doped. The substrate conductivity is typically in the range 0.1 to 50 ohm-cm because of residual impurities.
Although such SOI wafers are beneficial for most high speed circuits, they are not well suited for circuits that include integrated inductors. Inductors perform better when mounted on insulating or very highly resistive substrates. A typical SOI substrate does not provide such a substrate. There have been some published attempts to increase the substrate resistivity. For example, a group at Westinghouse has developed a process, in which very high purity (very high resistivity, of the order of 10 KOhm-cm) float-zone Si is used as the staring material for SIMOX. The same approach has been followed more recently by D. Figgert et al, xe2x80x9cA SOI-RF-CMOS Technology on High Resistivity SIMOX Substrates for Microwave Applications to 5 GHzxe2x80x9d, IEEE Trans. Electr. Dev., Vol. 44, p. 1981 (1997). Both teams have reported that circuits with improved performance can be built. However, there are problems with this method. The first problem is the difficulty of maintaining the very high purity of the float zone material through many high temperature steps required to make SOI wafers, and later the high temperature steps in the conventional device processing cycle. Any impurities inadvertently introduced into Si will diffuse at high processing temperatures throughout the wafer, making it more conductive. The second problem is that the float-zone process does not readily permit fabrication of large diameter wafers. Equipment for growing 150 mm silicon boules is only becoming available, and there are major technical challenges in scaling the process to larger diameters. In contrast, standard wafers made by the Czochralski or CZ process are readily available in 200 and 300 mm diameters and the semiconductor industry is starting conversion to 300 mm wafers. The third problem is that the cost of high purity float-zone wafers significantly exceeds that of CZ wafers.
An earlier SOI technique involved forming a silicon layer on a sapphire insulating substrate. This approach also used a relatively expensive substrate material, and the mechanical and thermal properties of the crystalline silicon film do not closely match those of the substrate.
Yet another approach is to abandon silicon technology and to fabricate the desired circuits in GaAs on a semi-insulating substrate. Unfortunately, GaAs technology is less developed and intrinsically much more expensive than silicon technology. Accordingly there is a need for an improved structure for high frequency integrated circuits.
In accordance with the invention, an integrated circuit comprising active and passive devices is formed in a thin slice of monocrystalline semiconductor bonded to a high resistivity polycrystalline silicon substrate. As compared with conventional integrated circuits supported on a monocrystalline substrate, circuits in monocrystalline films bonded to high resistivity polycrystalline substrates are less subject to parasitic capacitance, crosstalk and eddy currents. As compared with typical SOI wafers, the polycrystalline substrates have higher resistivity, and this resistivity is much less affected by contamination than it would be in monocrystalline substrates. Compared to silicon-on-sapphire or silicon on any other insulating material, the polycrystalline substrates are more compatible with the mechanical, thermal, and optical properties of the crystalline silicon layer.